Files
@ 15e507047bae
Branch filter:
Location: kallithea/rhodecode/public/js/mode/verilog/index.html - annotation
15e507047bae
3.4 KiB
text/html
Incorporate CSS from select2-bootstrap-css & its license information.
RhodeCode 2.2.5 included a modified version of this upstream work. We
include herein the upstream version as downloaded and incorporated using the
following commands:
(cd /tmp; \
git clone https://github.com/t0m/select2-bootstrap-css
)
cp /tmp/select2-bootstrap-css/select2-bootstrap.css rhodecode/public/js/select2/
The content used to be appended to select2.css but we now keep it in a separate
file select2-bootstrap.css . This file could be included in root.html like
select2.css but we do currently not want to use bootstrap.
The license info was incorporated from /tmp/select2-bootstrap-css/LICENSE
into our LICENSE.md file.
RhodeCode 2.2.5 included a modified version of this upstream work. We
include herein the upstream version as downloaded and incorporated using the
following commands:
(cd /tmp; \
git clone https://github.com/t0m/select2-bootstrap-css
)
cp /tmp/select2-bootstrap-css/select2-bootstrap.css rhodecode/public/js/select2/
The content used to be appended to select2.css but we now keep it in a separate
file select2-bootstrap.css . This file could be included in root.html like
select2.css but we do currently not want to use bootstrap.
The license info was incorporated from /tmp/select2-bootstrap-css/LICENSE
into our LICENSE.md file.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 | a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 c9bcfe2d2ade a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 c9bcfe2d2ade a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 a60a0e9092c6 | <!doctype html>
<html>
<head>
<meta charset="utf-8">
<title>CodeMirror: Verilog mode</title>
<link rel="stylesheet" href="../../lib/codemirror.css">
<script src="../../lib/codemirror.js"></script>
<script src="verilog.js"></script>
<link rel="stylesheet" href="../../doc/docs.css">
<style>.CodeMirror {border: 2px inset #dee;}</style>
</head>
<body>
<h1>CodeMirror: Verilog mode</h1>
<form><textarea id="code" name="code">
/* Verilog demo code */
module butterfly
#(
parameter WIDTH = 32,
parameter MWIDTH = 1
)
(
input wire clk,
input wire rst_n,
// m_in contains data that passes through this block with no change.
input wire [MWIDTH-1:0] m_in,
// The twiddle factor.
input wire signed [WIDTH-1:0] w,
// XA
input wire signed [WIDTH-1:0] xa,
// XB
input wire signed [WIDTH-1:0] xb,
// Set to 1 when new data is present on inputs.
input wire x_nd,
// delayed version of m_in.
output reg [MWIDTH-1:0] m_out,
// YA = XA + W*XB
// YB = XA - W*XB
output wire signed [WIDTH-1:0] ya,
output wire signed [WIDTH-1:0] yb,
output reg y_nd,
output reg error
);
// Set wire to the real and imag parts for convenience.
wire signed [WIDTH/2-1:0] xa_re;
wire signed [WIDTH/2-1:0] xa_im;
assign xa_re = xa[WIDTH-1:WIDTH/2];
assign xa_im = xa[WIDTH/2-1:0];
wire signed [WIDTH/2-1: 0] ya_re;
wire signed [WIDTH/2-1: 0] ya_im;
assign ya = {ya_re, ya_im};
wire signed [WIDTH/2-1: 0] yb_re;
wire signed [WIDTH/2-1: 0] yb_im;
assign yb = {yb_re, yb_im};
// Delayed stuff.
reg signed [WIDTH/2-1:0] xa_re_z;
reg signed [WIDTH/2-1:0] xa_im_z;
// Output of multiplier
wire signed [WIDTH-1:0] xbw;
wire signed [WIDTH/2-1:0] xbw_re;
wire signed [WIDTH/2-1:0] xbw_im;
assign xbw_re = xbw[WIDTH-1:WIDTH/2];
assign xbw_im = xbw[WIDTH/2-1:0];
// Do summing
// I don't think we should get overflow here because of the
// size of the twiddle factors.
// If we do testing should catch it.
assign ya_re = xa_re_z + xbw_re;
assign ya_im = xa_im_z + xbw_im;
assign yb_re = xa_re_z - xbw_re;
assign yb_im = xa_im_z - xbw_im;
// Create the multiply module.
multiply_complex #(WIDTH) multiply_complex_0
(.clk(clk),
.rst_n(rst_n),
.x(xb),
.y(w),
.z(xbw)
);
always @ (posedge clk)
begin
if (!rst_n)
begin
y_nd <= 1'b0;
error <= 1'b0;
end
else
begin
// Set delay for x_nd_old and m.
y_nd <= x_nd;
m_out <= m_in;
if (x_nd)
begin
xa_re_z <= xa_re/2;
xa_im_z <= xa_im/2;
end
end
end
endmodule
</textarea></form>
<script>
var editor = CodeMirror.fromTextArea(document.getElementById("code"), {
lineNumbers: true,
mode: "text/x-verilog"
});
</script>
<p>Simple mode that tries to handle Verilog-like languages as well as it
can. Takes one configuration parameters: <code>keywords</code>, an
object whose property names are the keywords in the language.</p>
<p><strong>MIME types defined:</strong> <code>text/x-verilog</code> (Verilog code).</p>
</body>
</html>
|